It is a constant endeavor to find ways of speeding up the rise and fall times of switching circuits. This is particularly a problem in circuits supplied from low voltage sources. The problem becomes more severe when employing voltage sources consisting of a battery which demands extremely low current drains.
Typical logic circuits employ a passive resistive load at their outputs. FIG. 1 shows a general diagram of a logic circuit 100 with an input 101 and an output 102, supplied from a power source 104. Often the logic circuit is driven by a current source, not shown in FIG. 1. In order to limit the power drain in such a circuit, the biasing current of the output stage is set as low as practical. An output stage with a bias current set at 0.1 mA, would require its load resistors, R.sub.L 106 to be relatively large, perhaps as high as 5 k ohm. Such high resistances are generally inefficient to implement in a VLSI process, and have relatively large parasitic capacitance associated with them. This furthermore results in a speed restricted circuit with outputs that can only rise exponentially with time constant R.sub.L C.sub.L, where C.sub.L 108 is the capacitive load on the output.
Attempts have been made to alleviate these problems with active load devices used in place of the load resistors. Each output resistor is replaced with a conventional constant-current biasing arrangement. However when such a circuit is implemented with MOS devices driven from a low supply voltage, the MOS devices are generally not saturated. Unsaturated MOS devices do not really behave as constant current sources. Effective operation of load replacement dictates a near ideal current source. In addition, the bias point of these MOS devices do not respond to the state of the gate, so the signal swing is not effectively controlled and the transition times are relatively slow. These same disadvantages result even when diode connected MOS devices are used as loads.